1. Field of the Invention
The present invention relates to a method and apparatus for buffering image data for motion compensation.
2. Description of the Related Art
Platforms for playing multimedia data such as video contents usually have a separate hardware accelerator therein. In particular, such a separate hardware accelerator is indispensable to a video codec because intensive data processing is required in the video codec. A motion compensation part of a video codec consumes the most amount of time in the video codec. In a video codec, the motion compensation part most frequently accesses data stored in a memory.
Thus, a majority of hardware accelerators include motion compensation parts. In order for a hardware accelerator to access data stored in a memory for motion compensation, several factors should be taken into account, such as an access unit and padding.
In general, most buses such as an advanced microprocessor bus architecture (AMBA) transmit data in units of 32 bits, and pixel data used for motion compensation is 8-bit data that is not memory-aligned. Thus, in order to improve the efficiency of a bus, 32-bit data has to be read in and data required for motion compensation has to be selected out of the read-in data in units of 8 bits. In all video codec standards, data for motion compensation can be accessed even when the current image deviates from a reference image. For data outside the range of the reference image, the values of pixels in the boundary portion of the reference image are used, which is called “padding”. The following two schemes are most widely used to implement a motion compensation part with hardware based on the two considerations.
First, a synchronous random access memory (SRAM) buffer is used as a buffer for motion compensation. In other words, in this scheme, data that has to be read by a motion compensation processor is previously placed in a provided separate SRAM buffer and then data stored in the SRAM buffer is used by the motion compensation processor after being padded if padding is necessary. However, according to this scheme, the size of hardware increases due to the separate SRAM buffer and the speed of motion compensation decreases because operations for motion compensation begin only after data of an entire block is stored in the SRAM buffer.
Second, a first-in first-out (FIFO) module based on one register array buffer is used as a buffer for motion compensation. In this scheme, 32-bit data is input and then is output as 8-bit data after being padded. The FIFO module uses a buffer formed by a combination of registers corresponding to the maximum width of a block for motion compensation, i.e., a single register array buffer. However, according to this scheme, the buffer is quickly filled up because 8 bits are output for 32-bit input data. Since new data cannot be input to the buffer until the remaining data of the buffer is completely output, the speed of motion compensation decreases.